In semiconductor memories an address for a memory cell is received as bi-level signals on a plurality of address lines. These binary address signals must be decoded in order to access a particular row and a particular column within the memory. A decoder is functionally a NOR circuit which generates an output on a selected row or column line with the address signal providing the inputs to the NOR circuit Various control signals are frequently applied to control the NOR circuit so that the proper address signals are received and the output is sequenced to occur at the proper time.
The decoder circuits heretofore used in semiconductor memories have functional adequately for relatively small memory sizes which operate at moderate speeds and powers. But new circuit techniques such as sharing both row and column addresses on the same lines and transmitting these to a row decoder at different times together with bootstrapping of a selected row line above the supply voltage have added new constraints to the design of a row decoder.